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71M6533/G/H and 71M6534/H Data Sheet
FDS_6533_6534_004
HIGH
HIGH-Z
LOW
MISSION
LCD/SLEEP
BROWNOUT
V3P3SYS
VBAT
V3P3D
DIO
HIGH
HIGH-Z
LOW
MISSION
LCD/SLEEP
BROWNOUT
V3P3SYS
VBAT
V3P3D
DIO
Not recommended
GNDD
Recommended
GNDD
Figure 9: Connecting an External Load to DIO Pins
1.5.8
LCD Drivers
o
o
o
o
The device contains a total of 57 (71M6533) or 75 (71M6534) dedicated and multiplexed LCD drivers,
which are grouped as follows:
? 15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 to SEG18, SEG20 to SEG23)
? 4 drivers multiplexed with the SPI port (SEG3 to SEG6)
? 2 drivers multiplexed with MUX_SYNC and CKTEST (SEG7 and SEG19)
? 3 or 8 drivers multiplexed with the ICE interface
71M6533 – 3 drivers (SEG9 to SEG11)
71M6534 – 8 drivers (SEG9 to SEG11 and SEG51 to SEG55)
71M6533 – 33 pins
71M6534 – 46 pins
With a minimum of 15 driver pins always available and a total of 57 (71M6533) or 75 (71M6534) driver
pins in the maximum configuration, the device is capable of driving between 60 to 228 pixels (71M6533)
or 60 to 300 pixels (71M6534) of an LCD display with 25% duty cycle. At eight pixels per digit, this
corresponds to 7.5 to 28 digits for the 71M6533 or 7.5 to 37 digits for the 71M6534. The LCD interface is
flexible and can drive 7-segment digits, 14- segments digits or enunciator symbols.
For each multi-use pin, the corresponding LCD_BITMAP [] bit (see Section 1.5.7 Digital I/O) is used to select
the pin for DIO or LCD operation. The mapping of the LCD_BITMAP [] bits is specified in Section 5.1 I/O
– COM3).
LCD segment data is written to the LCD_SEGn [3:0] I/O RAM registers as described in Section 5.2 I/O
RAM Description – Alphabetical Order . Note that even though the register names call out bit numbers 3
to 0 some registers use physical bits 4 to 7 .
The segment driver SEG18 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is controlled
by LCD_Y . There can be up to four pixels/segments connected to this driver pin. The I/O RAM field
LCD_BLKMAP18[3:0] identifies which pixels, if any, are to blink.
The LCD bias may be compensated for temperature using the LCD_DAC[2:0] bits in I/O RAM. The bias
may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and BROWNOUT
46
Rev 2
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